Adiabatic step-charging power-clock generator

Adiabatic logic families have been introduced as alternatives to conventional CMOS logic families in VLSI systems in order to improve on power and performance profiles. These adiabatic logic families reduce power consumption by recycling energy thanks to being synchronized and powered by a power-clock (PC) source, which facilitates the low-power, energy-recycling, adiabatic computation. Efficient Charge Recovery Logic (ECRL) is the adiabatic logic family that is focused on in this thesis. ECRL operates in four PC phases, each phase offset by 90 degrees, to provide the timing to, and act as the power source for, the ECRL circuit. This inherent pipelining eliminates the need of registers in the circuit, reducing area and time delays within the circuit. ECRL gates can implement the same Boolean functions as CMOS logic and still have substantial power savings, by about 50%, primarily due to the use of power clock circuits enabling recycling of the energy. Designing an energy efficient PC for adiabatic logic families remains largely unexplored in literature and there is a lack of analysis on the efficiency of the PC on adiabatic circuits.