Charge recovery circuits

Modern VLSI systems are under strict power and performance constraints, and the trade-offs between these two aspects drive industry and academic research alike. Static CMOS has been the leading logic family used in commercial VLSI systems for over a decade, but many alternatives exists and are currently being investigated. For example, some approaches propose to replace the kind of transistor devices used (e.g. TFET instead of MOSFET), or to use different materials (e.g. carbon nanotubes instead of silicon). At a higher level in the circuit design taxonomy, different logic families have been investigated (Dynamic circuits, Pass-transistor circuits, et cetera). A promising logic family, targeted at low-power consumption, is Charge Recovery Logic, or CRL, also known as adiabatic logic. CRL is a logic style aimed at reducing power consumption by recycling energy, and has been a growing topic of academic research for the past two decades. On one hand, CRL requires a paradigm shift in logic synthesis and design automation, and to this day no Electronic Design Automation tools exist that can take advantage of CRL's unique characteristics: The creation of such a tool needs methods and algorithms tailored to CRL. On the other hand, CRL energy-saving principles can be extended to mixed-signal circuits, e.g. comparators: this creates the new category of Charge Recovery Circuits. The union of the aforementioned fields of inquiry paves the road to fully adiabatic System-on-Chip (SOCs). This PhD dissertation presents results and methods that support the development of charge recovery SOCs. In the first part, CRL-specific algorithms are used to synthesize and compile large combinational logic circuits. Transistor-level simulations show that charge recovery logic is a feasible candidate to replace static CMOS for low-energy applications. In addition to these results, an EDA tool has been developed to provide the academic community with unprecedented access to system-level research. In the second part, an adiabatic analog comparator and a fully-adiabatic analog-to-digital-converter (ADC) are presented. Results show that the adiabatic principles can be successfully used to decrease the energy of mixed-signal circuits as well, with low impact on performance.