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Relating Friction in CMP to Topography Evolution
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Die-scale models of chemical-mechanical polishing (CMP) have been previously reported for a number of different CMP processes used in integrated circuit manufacturing, including oxide, dual material shallow trench isolation, and dual material copper damascene processes. These models can dynamically predict the evolution of surface topography (e.g., local feature step heights, film thickness nonuniformity across the different pattern density regions of the chip, dishing, and erosion) for any time point during CMP. This topography evolution information can be applied to better understand the basis for observed friction and wear in the CMP process. In this work, we explore models of the macroscopic frictional force based on the surface topography. CMP endpoint measurements, such as those from motor current traces, enable verification of model predictions relating friction to CMP surface topography evolution, for different types of CMP processes and patterned chips.
Title: Relating Friction in CMP to Topography Evolution
Description:
Die-scale models of chemical-mechanical polishing (CMP) have been previously reported for a number of different CMP processes used in integrated circuit manufacturing, including oxide, dual material shallow trench isolation, and dual material copper damascene processes.
These models can dynamically predict the evolution of surface topography (e.
g.
, local feature step heights, film thickness nonuniformity across the different pattern density regions of the chip, dishing, and erosion) for any time point during CMP.
This topography evolution information can be applied to better understand the basis for observed friction and wear in the CMP process.
In this work, we explore models of the macroscopic frictional force based on the surface topography.
CMP endpoint measurements, such as those from motor current traces, enable verification of model predictions relating friction to CMP surface topography evolution, for different types of CMP processes and patterned chips.
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