Search engine for discovering works of Art, research articles, and books related to Art and Culture
ShareThis
Javascript must be enabled to continue!

Reliability-Aware Voltage Scaling of Multicore Processors in Dark Silicon Era

View through CrossRef
With the technology scaling, multicore and many-core processors introduced themselves as an alternative to offset performance demands. Power and thermal constraints make remarkable area of chip underutilized, which is called the dark silicon in the literature. In this paper, we model a multicore processor based on Amdahl's Law and meanwhile consider both reliability issues and memory overheads. Then based on the accurate empirical results, we suggest effective voltage and frequency scaling under power constraints and different amount of dark silicon. Since power-efficient small cores result in more active cores in the multicore architecture, we attempt to improve the total performance by introducing more power-efficient multicore architectures along with decreasing the dark silicon percentage. According to the results, voltage scaling of the processor has negligible effect on performance of memory-intensive applications. However, performance of CPU-intensive applications is sensitive to voltage scaling, where for parallel and serial applications performance is improved and diminished, respectively. Energy and performance per watt of all applications are improved by voltage scaling.
Title: Reliability-Aware Voltage Scaling of Multicore Processors in Dark Silicon Era
Description:
With the technology scaling, multicore and many-core processors introduced themselves as an alternative to offset performance demands.
Power and thermal constraints make remarkable area of chip underutilized, which is called the dark silicon in the literature.
In this paper, we model a multicore processor based on Amdahl's Law and meanwhile consider both reliability issues and memory overheads.
Then based on the accurate empirical results, we suggest effective voltage and frequency scaling under power constraints and different amount of dark silicon.
Since power-efficient small cores result in more active cores in the multicore architecture, we attempt to improve the total performance by introducing more power-efficient multicore architectures along with decreasing the dark silicon percentage.
According to the results, voltage scaling of the processor has negligible effect on performance of memory-intensive applications.
However, performance of CPU-intensive applications is sensitive to voltage scaling, where for parallel and serial applications performance is improved and diminished, respectively.
Energy and performance per watt of all applications are improved by voltage scaling.

Related Results

Innovations in Multicore Network Processor Design for Enhanced Performance
Innovations in Multicore Network Processor Design for Enhanced Performance
The rapid expansion of network traffic, driven by the proliferation of internet-connected devices and the growing demand for high-speed data transmission, has intensified the need ...
Domination of Polynomial with Application
Domination of Polynomial with Application
In this paper, .We .initiate the study of domination. polynomial , consider G=(V,E) be a simple, finite, and directed graph without. isolated. vertex .We present a study of the Ira...
Runahead threads
Runahead threads
Los temas de investigación sobre multithreading han ganado mucho interés en la arquitectura de computadores con la aparición de procesadores multihilo y multinucleo. Los procesador...
Experiments in Multicore and Distributed Parallel Processing using JCSP
Experiments in Multicore and Distributed Parallel Processing using JCSP
It is currently very difficult to purchase any form of computer system be it, notebook, laptop, desktop server or high performance computing system that does not contain a multicor...
Probabilistically time-analyzable complex processor designs
Probabilistically time-analyzable complex processor designs
Industry developing Critical Real-Time Embedded Systems (CRTES), such as Aerospace, Space, Automotive and Railways, faces relentless demands for increased guaranteed processor perf...
Optimizing High-Speed Serial Links for Multicore Processors and Network Interfaces
Optimizing High-Speed Serial Links for Multicore Processors and Network Interfaces
In modern computing environments, high-speed serial links have become a critical component for ensuring efficient data transfer between multicore processors and network interfaces....
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems
Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-s...
Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors
Cost minimization of algorithms for scheduling parallel, single-threaded, heterogeneous, speed-scalable processors
We synthesize online scheduling algorithms to optimally assign a set of arriving heterogeneous tasks to heterogeneous speed-scalable processors under the single threaded computing ...

Back to Top