igh-speed Multiplier of Numbers Module for Public Key Cryptosystems

The features of the implementation of asymmetric cryptosystems and the need to implement them in hardware are considered. Based on the data encryption and decryption algorithm, the digital blocks are listed, where the basic operations of raising and multiplying numbers module are done. Various approaches to multiplying multi-digit numbers module are considered. A method of multiplying multi-digit numbers module is proposed. In each step, the multiplier is shifted to certain discharge in the direction of higher one with further reduction on the module. For this purpose, partial and intermediate residue formers, a multiplier of two bits of the multiplier for partial residues are introduced into the composition of the device. The advantage of this method is that there is no need for a preliminary calculation and the intermediate results of the calculation do not go beyond the bit grid of the module. In conclusion there is given an example for multiplying numbers module, where two digits of multiplier are analyzed on each step of the multiplier