Improving Temporal Characteristics of Mealy FSM with Composite State Codes

In this paper, we proposed a new state assignment method focusing on Mealy finite state machines (FSMs). The method makes it possible to improve the temporal characteristics of the circuits of FSMs, the internal states of which are encoded by the composite state codes (CSCs). These codes consist of class codes and partial state codes. Both class and partial state codes are maximum binary codes. We propose to encode classes by one-hot codes. The main goal of the method is improving the value of the FSM cycle time without any significant degradation of spatial characteristics. The method can be applied if FSM circuits are implemented using look-up table (LUT) elements of field-programmable gate arrays (FPGAs). The resulting FSM circuit includes two logic blocks. The first block generates partial input memory functions and FSM outputs depending on maximum binary state codes and one-hot class codes. The choice of partial codes allows minimizing the systems of partial functions. This allows generating most partial functions by single-LUT circuits. Some partial functions require using dedicated multiplexers. The second block generates final values of input memory functions and FSM outputs. This block does not require class codes to generate functions, which is the case of CSC-based FSMs. The proposed approach allows reducing the number of series-connected LUTs in comparison with CSC-based FSMs. Due to this reduction, the temporal characteristics are improved. The paper includes an example of FSM synthesis through applying the proposed method. The experiments are conducted using standard benchmark FSMs. The results of experiments show that the proposed method allows improving the temporal characteristics (by an average of 9.15%). In relation to CSC-based FSMs, the number of LUTs increases by an average of 10.03%, and the power consumption increases by an average of 7.63%.