Design of Approximate Restoring Dividers for Error Resilient Applications

In this paper, a low-power and high-speed approximate divider using restoring array architecture has been proposed. Approximation is realized by replacing the subtractor/divider cells with the approximate subtractor/divider cells through the use of reduced gate level complexity. Four approximate divider architectures, namely, AD1, AD2, AD3, and AD4, have been proposed. The amount of approximation can be scaled by introducing the approximation factor and the proposed dividers have been analyzed for different values of approximation factor. The simulation results show that the proposed dividers AD1, AD2, AD3, and AD4, with approximation factor of 10 have achieved power reduction of 17%, 30%, 23%, and 37% respectively, when compared to the exact restoring divider. The proposed dividers have also been compared with the existing approximate restoring divider and shows signification reduction in power and delay. All the simulations are carried out using 180nm CMOS technology. The image processing applications, such as change detection and background removal, have been implemented using the proposed divider to show the feasibility of employing the approximate divider for real time applications. The simulation results prove that the approximate dividers have realized a feasible PSNR for the resultant images.