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Fault Current Limitation (FCL) and Voltage Dip Improvement Thanks to Distributed Static Series Compensator (DSSC)
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This paper presents the comprehensive implementation of Distributed Static Series Compensator (DSSC) to limit the fault currents in power systems. This is the first time that the limitation of fault currents with D-FACTS devices is addressed. DSSC is one of the D-FACTS families whichoperate in a similar manner as Static Synchronous Series Compensator (SSSC) but in smaller size, lower price and more capability. The effectiveness of the DSSC in fault current limitation is investigated through the series voltage effect upon the line. The short circuit current limitation strategy presented here exhibited that besides of the power flow control which is carried out by DSSC; it can also perform this additional function. In the following the potency of the DSSC in reduction of instantaneous voltage dip range during fault current limiting mode is clarified. Furthermore, it is disclosed that with performing more DSSC in the power system, the entire system voltage dip will be improved. In order to validate the claims, computer simulations using PSCAD/EMTDC are exploited.
Title: Fault Current Limitation (FCL) and Voltage Dip Improvement Thanks to Distributed Static Series Compensator (DSSC)
Description:
This paper presents the comprehensive implementation of Distributed Static Series Compensator (DSSC) to limit the fault currents in power systems.
This is the first time that the limitation of fault currents with D-FACTS devices is addressed.
DSSC is one of the D-FACTS families whichoperate in a similar manner as Static Synchronous Series Compensator (SSSC) but in smaller size, lower price and more capability.
The effectiveness of the DSSC in fault current limitation is investigated through the series voltage effect upon the line.
The short circuit current limitation strategy presented here exhibited that besides of the power flow control which is carried out by DSSC; it can also perform this additional function.
In the following the potency of the DSSC in reduction of instantaneous voltage dip range during fault current limiting mode is clarified.
Furthermore, it is disclosed that with performing more DSSC in the power system, the entire system voltage dip will be improved.
In order to validate the claims, computer simulations using PSCAD/EMTDC are exploited.
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