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Method and VLSI implementation of lossy‐to‐lossless LTM ECG compression framework

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A lossy‐to‐lossless compression framework for electrocardiogram (ECG) signals is proposed for wearable monitoring devices. In this framework, the tail bits of the coefficients generated by the lifting discrete wavelet transform of the ECG sequences are truncated at different levels configured according to the tolerance of the information loss, while no truncation for lossless compression. These processed coefficients are then encoded with the modified run length code. The algorithm is evaluated by the MIT‐BIH arrhythmia database, where the experimental results show that the proposed framework achieves a better comprehensive performance than existing state‐of‐the‐art lossy‐to‐lossless compression approaches. The authors further demonstrate a three‐stage pipeline very large scale integration (VLSI) implementation of the compression framework, which can be used as an intellectual property core with a core area of 0.4 mm 2 and achieves power consumption of 1.524 μW at 360 Hz in a 0.18 μm CMOS technology.
Institution of Engineering and Technology (IET)
Title: Method and VLSI implementation of lossy‐to‐lossless LTM ECG compression framework
Description:
A lossy‐to‐lossless compression framework for electrocardiogram (ECG) signals is proposed for wearable monitoring devices.
In this framework, the tail bits of the coefficients generated by the lifting discrete wavelet transform of the ECG sequences are truncated at different levels configured according to the tolerance of the information loss, while no truncation for lossless compression.
These processed coefficients are then encoded with the modified run length code.
The algorithm is evaluated by the MIT‐BIH arrhythmia database, where the experimental results show that the proposed framework achieves a better comprehensive performance than existing state‐of‐the‐art lossy‐to‐lossless compression approaches.
The authors further demonstrate a three‐stage pipeline very large scale integration (VLSI) implementation of the compression framework, which can be used as an intellectual property core with a core area of 0.
4 mm 2 and achieves power consumption of 1.
524 μW at 360 Hz in a 0.
18 μm CMOS technology.

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