A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM

Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and ignorable leakage power. However, it suffers from the bad write latency and poor write power consumption. Relaxing the retention time of STT-RAM cell can improve the write performance, but volatile STT-RAM would dissipate extra energy due to frequent refresh operations. In this paper, we propose a methodology for L1 cache design with integrated SRAM and volatile STT-RAM architecture. Data block is mapped to SRAM firstly to reduce write latency, and is moved to volatile STT-RAM to reduce leakage power consumption. After a time period when there is no access of a data block in the volatile STT-RAM, we then stop its refresh operations to further reduce power consumption. Experimental results show that we get better energy consumption than fully SRAM based cache design because of less leakage energy, and also we have better memory access latency than fully STT-RAM cache architecture because of compatible write performance with SRAM.