Design and Stability analysis of CNTFET based SRAM cell

Abstract Carbon Nanotube Field Effect Transistor (CNTFET) has proved to be very beneficial for VLSI circuit designs in the nano scale range due to its amazing properties than MOSFETs. As we reduce the gate length of the device to below 45nm, we see a lot of changes in its parameters such as stability of the cell reduces, power consumption and delay increases which are different from the traditional MOSFETs. This becomes a serious issue when we try to take traditional MOSFETs scale down from this technology node. The main aim of this paper is to design CNTFET 6T SRAM memory cell which consumes less power and is highly stable at 32nm technology node. The Stanford model files have proved to be very good for the CNTFET devices, which simulates on 32 nm technology nodes in HSPICE tool. The results shown in this paper clearly indicate that the stability enhances by approx. 27.55% of the CNTFET SRAM cell with 37.44% improvement in the power consumption. Explicit analysis of the results shows that CNTFET based 6T SRAM cell has improved power consumption, less delay and high stability with improved read & write noise margin than conventional 6T SRAM cell.