VIRTUAL MEMORY VERIFICATION -SV32

Virtual memory compliance refers to the extent to which the behaviour of the virtual memory subsystem adheres to the specifications outlined in the RISC-V architecture. It ensures that the behavior of virtual memory operations, particularly the manipulation of permission bits within page table entries, aligns accurately with the documented expectations and standards of the RISC-V architecture. We developed customized RISC-V assembly tests that systematically modify permission bits within page table entries. These tests are compiled using GNU toolchain and executed using the RISC-V assembly code on both the Spike and Sail simulators through the RISCOF framework, facilitating cross-platform analysis. By comparing the resulting log files from the two simulators, we discern any inconsistencies or variations in memory access behaviors. The findings of this investigation provide insights into the fidelity of RISC-V architecture specifications with respect to virtual memory operations. We generally worked with two level page table in which first level is named as level 1 and second level is named as level 0. These outcomes are synthesized into a comprehensive HTML report, offering an in-depth exploration of permission bit effects on virtual memory within varying privilege modes. This research enhances comprehension of virtual memory functionality in the RISC-V architecture. This study contributes to a more robust understanding of virtual memory behavior and engenders confidence in the modeling and simulation of such systems.