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Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices

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In the realm of Internet of Things (IoT) security, the Physical Unclonable Function (PUF) emerges as a viable solution for generating individualized secure keys. These keys play a vital role in authentication, chip protection, and supply chain security, serving as crucial safeguards for resource-constrained IoT devices. This work introduces Boosted Configurable Ring Oscillator PUF (BC-PUF), an area-efficient variant of CROPUF that suits resource-constrained IoT devices. Additionally, BC-PUF employs an absorbent approach for the intermediate responses to optimize the utilization of CMOS delay configurations. Moreover, BC-PUF mitigates the risk of Machine Learning (ML)-based modeling attacks. BC-PUF is a multi-bit response architecture that has been developed, analyzed, and evaluated across 50 FPGAs, from each dataset of 10K Challenge-Response Pairs (CRPs) is extracted. Experimental results report average values of 50.2%, 40.4%, 42%, 3.925%, and 83% for uniformity, diffuseness, uniqueness, reliability, and Shannon entropy, respectively. In comparison to state-of-the-art designs, the BC-PUF design achieves area reductions ranging from 15% to 96.7% across various architectures and implementations, along with a power reduction of 9.7%. Moreover, BC-PUF demonstrates resilience against ML-based attacks, achieving a prediction accuracy of 51%.
Title: Boosted PUF: Boosting Efficiency and Resilience in Configurable RO PUF for IoT Devices
Description:
In the realm of Internet of Things (IoT) security, the Physical Unclonable Function (PUF) emerges as a viable solution for generating individualized secure keys.
These keys play a vital role in authentication, chip protection, and supply chain security, serving as crucial safeguards for resource-constrained IoT devices.
This work introduces Boosted Configurable Ring Oscillator PUF (BC-PUF), an area-efficient variant of CROPUF that suits resource-constrained IoT devices.
Additionally, BC-PUF employs an absorbent approach for the intermediate responses to optimize the utilization of CMOS delay configurations.
Moreover, BC-PUF mitigates the risk of Machine Learning (ML)-based modeling attacks.
BC-PUF is a multi-bit response architecture that has been developed, analyzed, and evaluated across 50 FPGAs, from each dataset of 10K Challenge-Response Pairs (CRPs) is extracted.
Experimental results report average values of 50.
2%, 40.
4%, 42%, 3.
925%, and 83% for uniformity, diffuseness, uniqueness, reliability, and Shannon entropy, respectively.
In comparison to state-of-the-art designs, the BC-PUF design achieves area reductions ranging from 15% to 96.
7% across various architectures and implementations, along with a power reduction of 9.
7%.
Moreover, BC-PUF demonstrates resilience against ML-based attacks, achieving a prediction accuracy of 51%.

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