Search engine for discovering works of Art, research articles, and books related to Art and Culture
Javascript must be enabled to continue!
A Low Power 9T SRAM Based In-Memory Computing Architecture for Single-Direction Logic and CAM Operations
View through CrossRef
We propose a novel 9-transistor (9T) Static Random Access Memory (SRAM) cell architecture that seamlessly integrates memory and logic operations, enabling a multifunctional computing paradigm. Unlike conventional SRAM designs that operate solely in a column-wise manner, our innovative cell supports full compatibility with standard memory systems. The proposed 9T SRAM cell operates in four distinct modes: Normal SRAM Mode, Logic Operations Mode, Binary Content-Addressable Memory (BCAM) Mode, Ternary Content-Addressable Memory (TCAM) Mode. Designed using 45nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, Our 9T SRAM cell achieves significant improvements in energy efficiency and speed, making it an attractive solution for Artificial Intelligence (AI) and security applications on edge devices. By integrating memory and logic functions, Our design reduces data transfer overhead, minimizes latency, and enhances overall system performance.
Title: A Low Power 9T SRAM Based In-Memory Computing Architecture for Single-Direction Logic and CAM Operations
Description:
We propose a novel 9-transistor (9T) Static Random Access Memory (SRAM) cell architecture that seamlessly integrates memory and logic operations, enabling a multifunctional computing paradigm.
Unlike conventional SRAM designs that operate solely in a column-wise manner, our innovative cell supports full compatibility with standard memory systems.
The proposed 9T SRAM cell operates in four distinct modes: Normal SRAM Mode, Logic Operations Mode, Binary Content-Addressable Memory (BCAM) Mode, Ternary Content-Addressable Memory (TCAM) Mode.
Designed using 45nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, Our 9T SRAM cell achieves significant improvements in energy efficiency and speed, making it an attractive solution for Artificial Intelligence (AI) and security applications on edge devices.
By integrating memory and logic functions, Our design reduces data transfer overhead, minimizes latency, and enhances overall system performance.
Related Results
A 7T SECURITY ORIENTED SRAM BITCELL USING VLSI
A 7T SECURITY ORIENTED SRAM BITCELL USING VLSI
Power analysis (PA) attacks have become a serious threat to security systems by enabling secret data extraction through the analysis of the current consumed by the power supply of ...
Low Power 8T and 9T SRAM Cell Configurations using Improved SVL (I-SVL)
Low Power 8T and 9T SRAM Cell Configurations using Improved SVL (I-SVL)
Background/Objectives: Memory is important in today's world of electronic equipment, such as processors and portable electronics, thanks to the use of static random-access memory (...
Reconfigurable In-Memory Computing Using Standard 6T SRAM for BCAM, TCAM, Similarity Indexing, and Logic-in-Memory Operations
Reconfigurable In-Memory Computing Using Standard 6T SRAM for BCAM, TCAM, Similarity Indexing, and Logic-in-Memory Operations
In-memory computing (IMC) has emerged as a promising paradigm to overcome the von Neumann bottleneck by performing computations directly within memory, thereby significantly reduci...
EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA
EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA
Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-p...
MECHANISMS OF SCHEMATIC MODELING BASED ON VECTOR LOGIC
MECHANISMS OF SCHEMATIC MODELING BASED ON VECTOR LOGIC
Context. This paper addresses issues relevant to the EDA market – reducing the cost and time of testing and verification of digital projects by synthesizing the logic vector of a d...
ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM
ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM
Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability...
Design, Testing, and Validation of SRAM Cells: From 6T to 10T Based on Identified Parameters
Design, Testing, and Validation of SRAM Cells: From 6T to 10T Based on Identified Parameters
Static Random Access Memory (SRAM) technology is the latest technology must advance to satisfy the high-speed performance and low power consumption requirements of contemporary dev...
Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit
Performance comparison of SRAM cells in 45NM technology in the presence of a memory cell control circuit
Lowering power consumption and increasing the noise margin have become the two most important aspects to be considered in SRAM design. Additionally, a stable operation with good me...