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A Low Power 9T SRAM Based In-Memory Computing Architecture for Single-Direction Logic and CAM Operations
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We propose a novel 9-transistor (9T) Static Random Access Memory (SRAM) cell architecture that seamlessly integrates memory and logic operations, enabling a multifunctional computing paradigm. Unlike conventional SRAM designs that operate solely in a column-wise manner, our innovative cell supports full compatibility with standard memory systems. The proposed 9T SRAM cell operates in four distinct modes: Normal SRAM Mode, Logic Operations Mode, Binary Content-Addressable Memory (BCAM) Mode, Ternary Content-Addressable Memory (TCAM) Mode. Designed using 45nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, Our 9T SRAM cell achieves significant improvements in energy efficiency and speed, making it an attractive solution for Artificial Intelligence (AI) and security applications on edge devices. By integrating memory and logic functions, Our design reduces data transfer overhead, minimizes latency, and enhances overall system performance.
Title: A Low Power 9T SRAM Based In-Memory Computing Architecture for Single-Direction Logic and CAM Operations
Description:
We propose a novel 9-transistor (9T) Static Random Access Memory (SRAM) cell architecture that seamlessly integrates memory and logic operations, enabling a multifunctional computing paradigm.
Unlike conventional SRAM designs that operate solely in a column-wise manner, our innovative cell supports full compatibility with standard memory systems.
The proposed 9T SRAM cell operates in four distinct modes: Normal SRAM Mode, Logic Operations Mode, Binary Content-Addressable Memory (BCAM) Mode, Ternary Content-Addressable Memory (TCAM) Mode.
Designed using 45nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, Our 9T SRAM cell achieves significant improvements in energy efficiency and speed, making it an attractive solution for Artificial Intelligence (AI) and security applications on edge devices.
By integrating memory and logic functions, Our design reduces data transfer overhead, minimizes latency, and enhances overall system performance.
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