Heterogeneous Uncore Architectures in Future Chip-Multi Processors

<p>Uncore components including on-chip memory systems and interconnects consume a significant portion of overall energy consumption in emerging embedded applications. Proposing new power-management techniques in future computing systems which consider the impact of power consumption of core and uncore components, simultaneously, is largely unexplored.</p> <p>A set of comprehensive motivational observations on the importance of uncore power consumption in comparison to core components have been demonstrated in Chapters 1 and 2. After the motivational chapters, the structure of this thesis has been divided into two parts. The first part, including Chapters 3, 4, and 5, proposes energy-efficient heterogeneous architectures using optimization and machine learning-based techniques. In the second part, Chapter 6, an energy-aware machine learning-specific manycore with heterogeneous uncore has been proposed. The aim of Chapter 6 is improving the energy efficiency of machine learning algorithms by running on new specific multi-manycore systems for applying them in Chapters 3, 4, and 5 to propose new architectures. There is a positive feedback loop between the two parts of the thesis.</p> <p><br></p> <p>In Chapter 3, a design-time approach based on a convex optimization model has been proposed to architect an energy-aware heterogeneous uncore architecture in multi-manycore systems. This design-time approach shows 47.4% energy improvement with 3.2% performance degradation in comparison to an SRAM architecture. In Chapter 4, the first runtime approach using performance counters has been proposed to design an adaptive energy-aware heterogeneous uncore architecture. In Chapter 5, the second runtime approach using a machine learning algorithm has been proposed to design another adaptive energy-aware heterogeneous uncore architecture in multi-manycore systems. The proposed runtime approaches improve energy by about 45.2% and enhance performance by about 13%, on average, in comparison to pure SRAMs. At the end of Chapter 5, the design-time approach proposed in Chapter 3 and first and second runtime approaches proposed in Chapters 4 and 5 have been compared. This comparison shows that for CPU-bound applications, the design-time architecture shows better energy efficiency, while it is the opposite in memory-bound applications. The first and second runtime approaches demonstrate 12% and 17% energy-delay product improvement in comparison to the design-time, on average.</p>