Trace2PatchLR: Reproducible RTL Bug Localization and Template-Guided Repair for Verilog Debug

Register-transfer level (RTL) debug dominates the turnaround time of modern chip development: after simulation or formal verification reports a failure, engineers must localize the faulty RTL statement and craft a repair that restores functional correctness. This work presents a fully reproducible study of automated RTL bug localization and template-guided repair on RTLMutBench, a benchmark of 1,050 single-bug Verilog modules spanning combinational datapath logic, sequential counters, and finite-state machines. Each design includes a deterministic test suite with statement-level coverage and a reference fix. We evaluate spectrum-based fault localization (Tarantula and Ochiai), static slicing, and a lightweight learning-to-rank model (Trace2PatchLR) that combines coverage statistics, slicing membership, and lexical features. On the held-out test split, Trace2PatchLR attains 94.3% Top-1 localization accuracy and 0.965 mean reciprocal rank, outperforming Ochiai (76.2% Top-1, 0.839 MRR) and Tarantula (81.9% Top-1, 0.881 MRR). We then connect localization to repair via a template-guided patch search space derived from common RTL mistake patterns. The resulting Trace2PatchRepair fixes 95.2% of failing designs within 12 candidate patches (median 2 attempts), compared to 86.7% for OchiaiRepair and 28.6% for RandomRepair. All results, tables, and figures in this manuscript are generated from the released dataset generator and experiment scripts under a fixed random seed.