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A CMOS silicon spin qubit

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AbstractSilicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.
Title: A CMOS silicon spin qubit
Description:
AbstractSilicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors.
Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware.
Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process.
The device consists of a two-gate, p-type transistor with an undoped channel.
At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out.
All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate.
The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

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