Multiscale thermal modeling of advanced back-end-of-line stacks considering size effects and nanoscale interfaces

As technology nodes scale down, back-end-of-line (BEOL) interconnects in integrated circuits (ICs) constitute a significant thermal barrier that impedes heat removal in advanced packaging. Accurate thermal modeling is therefore essential to enable better thermal design of the BEOL. However, existing studies often neglect size effects and interfacial resistance when metal linewidths reach the nanometer scale, leading to inaccurate predictions of BEOL thermal behavior at advanced nodes. To overcome these limitations, we developed a multiscale thermal modeling framework that spans from the atomic to metallization level to explicitly capture nanoscale thermal transport phenomena. Using this framework, we systematically analyzed the BEOL thermal performance with different design parameters and metallization schemes across various technology nodes. We find that the effective out-of-plane thermal conductivity of the BEOL stack degrades significantly with node scaling, dropping by over 50% from N90 to N5 node. The interfacial thermal resistances for metal-dielectric interfaces are calculated to be in the range of 2.5-6.5×10-8 m2K·W-1, which is consistent with literature estimates. We demonstrate that neglecting these nanoscale interfaces leads to an overestimation of BEOL thermal conductivity by nearly 40% at advanced nodes. Through sensitivity analyses, we reveal that via density and dielectric thermal conductivity strongly impact the BEOL thermal performance, where optimizing these factors can yield a thermal resistance reduction of over 50%. Furthermore, a comparative assessment of advanced metallization schemes suggests that Ruthenium (Ru) is the most promising post-Cu candidate in terms of thermal capability. This work elucidates the critical role of nanoscale interfaces in BEOL thermal performance and provides pivotal insights for the thermal design of emerging backside power delivery architectures in future 3D ICs.