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(Invited) Characterization of Interface Defects by the Charge Pumping Technique
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Charge pumping (CP) technique [1] is known to be a highly-precise method for evaluating the density of interface traps between the gate oxide and the semiconductor surface in MOSFETs, and the method has been widely used for the last 30 years. Applying the method, it has been reported that various information on the interface and the near-interface defects can be obtained, such as the density of the states of interface traps [2], the capture cross sections of interface traps using the three-level CP method [3, 4], observation of near-interface oxide traps [5] and the depth concentration profile of the oxide traps [6], observation of the recovery of interface traps by a first single pulse CP technique [7], determination of the spatial distribution of hot-carrier-induced fixed charge near the drain [8], and so on.
Besides the MOS interface or near-interface traps, we have successfully evaluated the density of the interface traps in a SiGe/Si heterostructure introduced into the channel region of Si MOSFETs using a low-temperature CP method, avoiding interference from the interface traps between the gate oxide and the semiconductor surface [9]. A good correlation was obtained between the measured density of interface traps in the heterostructure and low-frequency noise level in the current flowing in the SiGe-channel. Moreover, hot carrier degradation at the nanometer-thick heterostructures was also evaluated using the low-temperature CP method, and the width of the damaged heterointerface region and the density of the locally generated heterointerface traps were successfully estimated [10].
Recently, we have developed effective procedures to detect and characterize single MOS interface traps by the CP method, and found that two energy levels participate in electron capture/emission processes in a single trap, therefore, the maximum CP current per trap (I
CPMAX) is in the range of 0≦I
CPMAX≦2fq, but not a fixed value of fq (f: the gate pulse frequency, q: the electron charge) [11]. Therefore, it was found that the conventional CP theory is basically incorrect. This finding supports that the origin of the interface traps is P
b centers, and it has been experimentally clarified that the various values of I
CPMAX result from the differences in the pairs of donor-like and acceptor-like trap energy levels. The single-interface-trap density of the states has been also experimentally obtained, which is reasonably similar to the P
b0 density of the states.
Acknowledgments
This work was partially supported by the Grants-in-Aid for Scientific Research No. 26289105 from the JSPS.
References
[1] G. Groeseneken et al., IEEE Trans. Electron Devices 31, 42 (1984).
[2] G. Van den bosch et al., IEEE Trans. Electron Devices 38, 1820 (1991).
[3] N. S. Saks and M. G. Ancona, IEEE Electron Device Lett., 11, 339 (1990).
[4] L. Militaru et al., IEEE Electron Device Lett., 23, 94 (2002).
[5] R. E. Paulsen et al., IEEE Electron Device Lett., 13, 627 (1992).
[6] D. Bauza and Y. Maneglia, IEEE Trans. Electron Devices, 44, 2262 (1997).
[7] L. Lin et al., IEEE Trans. Electron Devices 58, 1490 (2011).
[8] M. Tsuchiaki et al., IEEE Trans. Electron Devices 40, 1768 (1993).
[9] T. Tsuchiya et al., IEEE Trans. Electron Devices 50, 2507 (2003).
[10] T. Tsuchiya et al., Jpn. J. Appl. Phys. 46 (8A), 5015 (2007).
[11] T. Tsuchiya and Y. Ono, Jpn. J. Appl. Phys. 54 (4S), 04DC01 (2015).
Title: (Invited) Characterization of Interface Defects by the Charge Pumping Technique
Description:
Charge pumping (CP) technique [1] is known to be a highly-precise method for evaluating the density of interface traps between the gate oxide and the semiconductor surface in MOSFETs, and the method has been widely used for the last 30 years.
Applying the method, it has been reported that various information on the interface and the near-interface defects can be obtained, such as the density of the states of interface traps [2], the capture cross sections of interface traps using the three-level CP method [3, 4], observation of near-interface oxide traps [5] and the depth concentration profile of the oxide traps [6], observation of the recovery of interface traps by a first single pulse CP technique [7], determination of the spatial distribution of hot-carrier-induced fixed charge near the drain [8], and so on.
Besides the MOS interface or near-interface traps, we have successfully evaluated the density of the interface traps in a SiGe/Si heterostructure introduced into the channel region of Si MOSFETs using a low-temperature CP method, avoiding interference from the interface traps between the gate oxide and the semiconductor surface [9].
A good correlation was obtained between the measured density of interface traps in the heterostructure and low-frequency noise level in the current flowing in the SiGe-channel.
Moreover, hot carrier degradation at the nanometer-thick heterostructures was also evaluated using the low-temperature CP method, and the width of the damaged heterointerface region and the density of the locally generated heterointerface traps were successfully estimated [10].
Recently, we have developed effective procedures to detect and characterize single MOS interface traps by the CP method, and found that two energy levels participate in electron capture/emission processes in a single trap, therefore, the maximum CP current per trap (I
CPMAX) is in the range of 0≦I
CPMAX≦2fq, but not a fixed value of fq (f: the gate pulse frequency, q: the electron charge) [11].
Therefore, it was found that the conventional CP theory is basically incorrect.
This finding supports that the origin of the interface traps is P
b centers, and it has been experimentally clarified that the various values of I
CPMAX result from the differences in the pairs of donor-like and acceptor-like trap energy levels.
The single-interface-trap density of the states has been also experimentally obtained, which is reasonably similar to the P
b0 density of the states.
Acknowledgments
This work was partially supported by the Grants-in-Aid for Scientific Research No.
26289105 from the JSPS.
References
[1] G.
Groeseneken et al.
, IEEE Trans.
Electron Devices 31, 42 (1984).
[2] G.
Van den bosch et al.
, IEEE Trans.
Electron Devices 38, 1820 (1991).
[3] N.
S.
Saks and M.
G.
Ancona, IEEE Electron Device Lett.
, 11, 339 (1990).
[4] L.
Militaru et al.
, IEEE Electron Device Lett.
, 23, 94 (2002).
[5] R.
E.
Paulsen et al.
, IEEE Electron Device Lett.
, 13, 627 (1992).
[6] D.
Bauza and Y.
Maneglia, IEEE Trans.
Electron Devices, 44, 2262 (1997).
[7] L.
Lin et al.
, IEEE Trans.
Electron Devices 58, 1490 (2011).
[8] M.
Tsuchiaki et al.
, IEEE Trans.
Electron Devices 40, 1768 (1993).
[9] T.
Tsuchiya et al.
, IEEE Trans.
Electron Devices 50, 2507 (2003).
[10] T.
Tsuchiya et al.
, Jpn.
J.
Appl.
Phys.
46 (8A), 5015 (2007).
[11] T.
Tsuchiya and Y.
Ono, Jpn.
J.
Appl.
Phys.
54 (4S), 04DC01 (2015).
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