(Invited) Dielectric Science on Today's Devices

Device scaling in CMOS technology has approached to 10nm range and below. The gate dielectric, being the critical constraint, has evolved significantly and requires constant quality improvements in order to keep the proper functioning of the transistors and memory devices. While the transistor has transformed from a planar device to a three-dimensional device to a gate all around device, several new devices such as ferroelectric FETs and negative capacitance FETs have emerged to be integrated into standard CMOS technology. Additionally, many forms of memory devices such as resistive random-access memory (ReRAM) devices and ferroelectric RAM devices are being investigated for possible implementation of artificial intelligence hardware. All these devices use high dielectric constant (high-k) materials in some form or other. The electrical performance in these devices depends on the dielectric deposition process, precise selection of deposition parameters, pre-deposition surface treatments and subsequent thermal budget. In this work we describe the evolution of dielectric science in nanoelectronics. For logic devices, once the thickness of SiO2 reached the onset of direct tunneling region (<1.5 nm) high-k insulators were introduced to suppress the direct-tunneling leakage current. Because of thermal stability, HfO2-based high-k dielectrics were selected to replace SiO2. To resolve issues like mobility degradation, threshold voltage control and Fermi-level pinning, HfO2-based high-k gate dielectrics was introduced with an interfacial SiO2 layer on silicon devices. Subsequently, higher-k dielectrics are required for transistors performance enhancement to keep up with the scaling without reducing the physical dielectric thickness. It was achieved by controlling the structural phase of HfO2 by doping HfO2 with various metal oxides including ZrO2 as cubic, or tetragonal phase that provides higher-k than amorphous or monoclinic phase. By considering the interface reaction kinetics and thermal budget various atomic layer deposition (ALD) schemes were identified to get a stable dielectric with a robust interface. We will discuss the deposition of Hf1-xZrxO2 or HfAlOx on both silicon and germanium, a higher mobility channel material. The reliability characterization of these dialectics based on dielectric-semiconductor interface will also be discussed. In ReRAM devices, the resistance change, achieved in a dielectric material between two metal terminals by applying a voltage, is promising for further scaling of memory devices. The switching mechanism in transition metal oxides like HfO2 is, while evolving, based on similar mechanism to soft breakdown, where a conducting filament path is formed due to oxygen vacancy transition/formation. The process is reversed by rupturing the filament. Various dielectric stacks are currently being studied for ReRAM applications. Additionally, ferroelectric characteristics of HfZrO films also derived significant attention recently. Some of the current trends in memory devices involving high-k dielectrics will be discussed.