AI-Assisted Low Power Optimization in CMOS VLSI Circuits Using Machine Learning Technique

The rapid growth of portable electronic devices, Internet of Things devices, and embedded systems has made power consumption a critical constraint in the design of modern Very Large Scale Integration (VLSI) systems. Manual design cycles and simulation time are important parts of traditional circuit optimization techniques, which are computationally intensive. In order to optimize the power consumption in the case of CMOS VLSI circuits while maintaining the delay and area properties, the present study proposes a machine learning-based optimization technique. Inverters, full adders, and multiplexers are examples of basic CMOS VLSI circuits that are used to design the simulation dataset. Machine learning models are used to analyze the simulation dataset in order to find the optimal design parameters such as switching activities, voltage levels, and transistor sizes. Based on the simulation results, the proposed ML-based optimization approach has the advantage of reducing power consumption by 20-28% compared to the traditional methods of designing circuits with minimal delay overhead. The proposed approach could be utilized in the context of embedded systems, low-power processors, IoT devices, and efficient computing platforms.