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Neural-Model-Augmented Hybrid NMS-OSD Decoders for Near-ML in Short Block Codes
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Abstract
This paper introduces a hybrid decoding architecture that serially couples a normalized min-sum (NMS) decoder with reinforced ordered statistics decoding (OSD) to achieve near-maximum likelihood (ML) performance for short linear block codes. The framework incorporates several key innovations: a decoding information aggregation model that employs a convolutional neural network to refine bit reliability estimates for OSD using the soft-output trajectory of the NMS decoder; an adaptive decoding path for OSD, initialized by the arranged list of the most a priori likely tests algorithm and dynamically updated with empirical data; and a sliding window assisted model that enables early termination of test error patterns’ traversal, curbing complexity with minimal performance loss. For short high-rate codes, a dedicated undetected error detector identifies erroneous NMS outcomes that satisfy parity checks, ensuring they are forwarded to OSD for correction. Extensive simulations on LDPC, BCH, and RS codes demonstrate that the proposed hybrid decoder delivers a competitive trade-off, achieving near-ML frame error rate performance while maintaining advantages in throughput, latency, and complexity over state-of-the-art alternatives.
Title: Neural-Model-Augmented Hybrid NMS-OSD Decoders for Near-ML in Short Block Codes
Description:
Abstract
This paper introduces a hybrid decoding architecture that serially couples a normalized min-sum (NMS) decoder with reinforced ordered statistics decoding (OSD) to achieve near-maximum likelihood (ML) performance for short linear block codes.
The framework incorporates several key innovations: a decoding information aggregation model that employs a convolutional neural network to refine bit reliability estimates for OSD using the soft-output trajectory of the NMS decoder; an adaptive decoding path for OSD, initialized by the arranged list of the most a priori likely tests algorithm and dynamically updated with empirical data; and a sliding window assisted model that enables early termination of test error patterns’ traversal, curbing complexity with minimal performance loss.
For short high-rate codes, a dedicated undetected error detector identifies erroneous NMS outcomes that satisfy parity checks, ensuring they are forwarded to OSD for correction.
Extensive simulations on LDPC, BCH, and RS codes demonstrate that the proposed hybrid decoder delivers a competitive trade-off, achieving near-ML frame error rate performance while maintaining advantages in throughput, latency, and complexity over state-of-the-art alternatives.
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