Have you Designed for Manufacturing Test?

ABSTRACT Current trends in chip design promote the concept of Designed for Test (DfT) and Designed for Manufacturing (DfM). With DfT, designers add scan chains and, built-in self-test (BIST) structures, etc., which ease the job of test engineers in silicon fault detection. On the other hand, DfM puts in place rules that will enable very quick ramps to high volume production with multiple designs in multiple fabs. As noted by Intel's Clair Webb in the Intel Technology Journal, “The design and process have to be manufacturable at the beginning of the ramp. Design rules have to be defined early in the process development work to allow product design to be done in parallel with the process development [1].” Webb's statements are commonplace in the front end of the chip design process (Figure 1), but do not guarantee a design that is ready for manufacturing test or high-volume test. For a chip to be “designed for manufacturing test” (DfMT) early in the process, the designer must consider the capabilities and limitations of the manufacturing test facility and design accordingly. Furthermore, if the designed chip is assembled and tested at an outsourced semiconductor assembly and test (OSAT) factory, it is important for the chip designer to align with the OSAT mindset. This paper describes the OSAT mindset, constraints and capabilities of the manufacturing test floor. It also discusses several types of testing options such as wafer-sort, partially-assembled test, final test, and system-level test. It also examines how the test specifications and the addition of test insert points can affect the cost of the product.