Disbursed control computer architecture

Disbursed Control Computer Architecture, comprising totally pipelined computer, a number of components interconnected in a pipeline:Control storage for control and input-output address maker, plurality of other control storage for corresponding plurality of data address makers, and another control storage for operators and operational registers.Any mentioned control storage contains, as a part of a program, a plurality of appropriate section of a control word. Control and input-output address maker issues control address to all mentioned control storage and receives its own section of control word.Plurality of data address makers receives plurality of corresponding sections of control word and issue corresponding plurality of data addresses to operands and results storage, which, in turn, is issuing and receiving data to and from operational registers and bus joint and to condition and status logic.Each clock cycle, new control address initiates new control word, sections of which contain all commands and addresses for enactment of next control and input-output address, by control and input-output address maker, and of next plurality of data addresses, by plurality of data address makers.Following in pipeline, new commands and data submitted to operators and operational registers direct performance of new primary (originated by the task) operations every clock cycle.Several clock cycles are allotted along pipeline to data address makers, allowing the most complex address preparations.Also comprising: interconnect of totally pipelined computer with other computers, operating via input-output devices with separate sending and receiving ports.