VHDL-Based Low-Power Modem Design Using QPSK and IIR Filters on Xilinx FPGA

This paper presents a low-power modem realized using Quadrature Phase Shift Keying (QPSK) modulation and Infinite Impulse Response (IIR) filters on a Xilinx FPGA. The architecture, designed for low-power wireless communication in mobile handsets, IoT, and battery-powered applications, incorporates 16−bit fixed-point IIR filters with power consumption of 40 mW. Adaptive voltage scaling reduces energy by another 15%, and clock gating and Dynamic Voltage Scaling (DVS) reduce total power consumption by up to 30%. Hardware-in-the-Loop (HIL) Bit Error Rate (BER) testing and in-situ power measurements confirm 98 mW total system power at 12 dB SNR, with a BER of 1.2 × 10−6. Compared to Finite Impulse Response (FIR)-based implementations, the new modem has 35% less latency and improved computational efficiency. The FPGA design is scalable and parallel-processing capable, making it easily implementable in real-time applications such as sensor networks, mobile communication, and SDR systems. The QPSK modulation is very efficient in terms of spectra, transmitting two bits per symbol and yet being extremely robust in noisy environments. The integration of the IIR filter also enhances signal quality by filtering out noise and optimizing the use of hardware resources. A comparative analysis explains the modem’s higher power efficiency, lower computational complexity, and superior performance over state-of-the-art designs. Future research efforts will consider adaptive modulation schemes, i.e., Orthogonal Frequency Division Multiplexing (OFDM), for spectral efficiency enhancement, and machine learning-based dynamic power management and hardware acceleration for further optimization. The suggested design provides a power-saving solution for next generation wireless communication, especially in systems with constrained energy resources.