Optoelectronic Frequency Stabilization Techniques in Forced Oscillators

Forced frequency stabilization techniques of self-injection locking (SIL) and self-phase locked loop (SPLL) have been demonstrated to be effective for phase noise reduction. In SIL scheme, a portion of the oscillator output is directly injected back to the oscillator after passing through a long delay while in SPLL, the delayed signal is used to compare against a non-delayed signal to generate an error signal which will be used to control the oscillator frequency. The published literature and reported patent investigations has revealed that SIL and SPLL are only being used independently, whereas in this thesis SILPLL is introduced for the first time by simultaneously combining of SIL and SPLL; the control theory based modeling of SIL, SPLL, and SILPLL techniques are developed and the simulation results have indicated that phase noise of the oscillation signal is enhanced as injection locking removes phase noise in far-out offset frequency, while phase locking effectively reduces the close-in to carrier phase noise. Optimum delay length and delay parameters are identified for the most effective performance. Both SIL and SPLL techniques require a low noise figure and long fiber optic delay lines to provide substantial phase noise reduction, but the long delay generates undesirable sidemodes that are seen within 20kHz to 200kHz offset to carrier for fiber optic delays from 10km to 1km and are difficult to be filtered out by electrical filters. Therefore, forced oscillation technique employing short and long delay is proposed to suppress these sidemodes. In this dissertation, experimental results of a dual self-injection locking (DSIL) and dual self-phase locked loop (DSPLL) employing short and long delays have been proposed for this sidemode suppression, while maintaining same amount of phase noise reduction provided by the long delay. As an example of DSIL, sidemode suppression of more than 20dB for fiber delay links of 1km and 5km have been experimentally achieved compared to a single 5km long SIL with a phase noise reduction of 40dB (in reference to free running oscillator) at 10kHz offset from carrier for both standard OEO and a self-seeded structure with electrical 3 port oscillator at 10GHz; for a DSPLL fiber delay lines of 3km and 5km, a sidemode suppression of 29dB have also been experimentally achieved compared to SPLL of 5km with a phase noise reduction of 30dB (in reference to free running oscillator) at 10kHz offset from carrier. For the case of SPLL, phase locking performance of a 10GHz oscillation signal are experimentally evaluated as various methods of phase locking are compared. Experiment results that demonstrate the benefit of SILPLL incorporating dual delays have been reported for the first time corroborating analytical predictions. A dual SILPLL (DSILPLL) system with 3km and 5km fiber delay has been implemented, and measured phase noise reduction of 40dB provided by DSILPLL is the same as DSIL at 10kHz offset. However, at 1kHz offset, DSILPLL provides a phase noise reduction of 52dB which is 11dB better than DSIL; at 300Hz offset, DSILPLL provides 70dB reduction while DSIL provides only 42dB reduction. In summary, DSILPLL is effective for sidemode suppression and phase noise reduction, where SPLL using tunable MZM with DSIL of a VCO provides the best performance improvement over other investigated topologies. Due to the advances in low noise electronics and broad bandwidth of the optical components used in the DSILPLL system, the DSILPLL technique has the potential to create highly stable RF oscillators approaching 100GHz.