Functionally Undetectable Interconnect Faults in Chiplet-Based Designs

Chiplet-based designs use large numbers of interconnects that need to be tested thoroughly. Standard isolation logic allows the logic blocks (chiplets) and the interconnects to be tested separately. It was recently suggested for additional defect coverage to use a scan-based test set that tests the interconnects together with the logic blocks in a mode of operation that is closer to functional. In this scenario, a scan-based test set for a logic block targets faults in the logic block as well as the interconnects it drives. An exhaustive static fault model was used earlier for subsets of adjacent interconnects. In the same scenario, this article studies the presence of functionally undetectable interconnect faults, and their relationship to the configuration of the interconnects as a two-dimensional array. The article observes that the specific configuration of the interconnects in the two-dimensional array can affect the number of functionally undetectable faults. Moreover, by modifying the configuration, it is possible to eliminate functionally undetectable faults that are important to consider in other configurations. The article describes a test generation procedure that includes the identification of functionally undetectable interconnect faults, and a procedure for reconfiguring the interconnects to eliminate undetectable faults. The implementation of the procedures was carried out in an academic simulation environment. Experimental results for benchmark circuits demonstrate the effectiveness of the procedures in achieving complete interconnect fault coverage, and eliminating all the undetectable interconnect faults.