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Towards a Software Transactional Memory for Heterogeneous CPU-GPU Processors
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The heterogeneous Accelerated Processing Units (APUs) integrate a multi-core CPU and a GPU within the same chip. Modern APUs provide the programmer with platform atomics, used to communicate the CPU cores with the GPU using simple atomic datatypes. However, ensuring consistency for complex data types is a task delegated to programmers, who have to implement a mutual exclusion mechanism. Transactional Memory (TM) is an optimistic approach to implement mutual exclusion. With TM, shared data can be accessed by multiple computing threads speculatively, but changes are only visible if a transaction ends with no conflict with others in its memory accesses. TM has been studied and implemented in software and hardware for both CPU and GPU platforms, but an integrated solution has not been provided for APU processors.
Title: Towards a Software Transactional Memory for Heterogeneous CPU-GPU Processors
Description:
The heterogeneous Accelerated Processing Units (APUs) integrate a multi-core CPU and a GPU within the same chip.
Modern APUs provide the programmer with platform atomics, used to communicate the CPU cores with the GPU using simple atomic datatypes.
However, ensuring consistency for complex data types is a task delegated to programmers, who have to implement a mutual exclusion mechanism.
Transactional Memory (TM) is an optimistic approach to implement mutual exclusion.
With TM, shared data can be accessed by multiple computing threads speculatively, but changes are only visible if a transaction ends with no conflict with others in its memory accesses.
TM has been studied and implemented in software and hardware for both CPU and GPU platforms, but an integrated solution has not been provided for APU processors.
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