Thermal Effects in High Compactness CEA Stack

Thermal management is a pivotal aspect of stack durability and system operability. Consequently, understanding the thermal mapping within a stack based on its operating conditions is essential. Due to the compact design of the CEA stack, it is typically instrumented with thermocouples only at the end plates, which is insufficient to precisely characterize the stack's inner temperature. To gain a more thorough insight into the stack operando thermal field, a specialized experiment was conducted. A 22-cell, 200 cm² stack (CEA compact architecture) was equipped with 42 additional thermocouples placed inside the stack using three specifically designed plates inserted at various locations within the stack. This setup allowed for the measurement of highly localized temperature variations during the test. Thermal mapping was observed during standard stack operations in SOEC mode, including polarization curves and thermoneutral operating points. Polarization curves obtained at different current ramps highlighted significant internal cooling within the stack during the process. Additionally, a notable temperature gap was observed between the temperatures inside the stack and those measured at the end plates, particularly at low current ramps. Specific measurements were conducted, such as a thermalized polarization curve with thermal stabilization at each current step. The thermal maps obtained during this test showed a maximum deltaT of 37°C within the same plate and a 40°C deltaT between the central plate and the end plates. The experiment revealed that the most homogeneous thermal mapping is achieved at an average voltage lower than the thermoneutral voltage (~1.27V compared to 1.285V). Other specific tests were carried out, including an operating point with a high endothermal power value (-19.4W/cell) that remained stable for 120 hours with a deltaT of 34°C inside the central thermal plate. This experiment demonstrated that the use of such thermal plates enables the measurement of in situ temperatures and revealed significant discrepancies between the temperatures at the core and at the end plates, which are typically used to operate the stacks. To complement this experimental work, the development of a 3D numerical model is underway to achieve correlation. Introduction The European Commission’s roadmap for achieving a competitive low-carbon economy by 2050 necessitates a rethinking of clean energy supply policies across all economic sectors [1]. Hydrogen emerges as a pivotal player, serving as a resource for industrial processes, a transportation fuel, and a medium for high-capacity and long-distance electricity storage [2]. Hydrogen's share in the European energy mix is expected to rise from less than 2% currently to 13-14% by 2050 [3]. In light of this trajectory, increasing carbon-free hydrogen production, mainly through water electrolysis, is crucial. Among various electrolysis technologies, Solid Oxide Electrolysis (SOE) stands out for its efficiency, promising low-cost hydrogen production and forecasts predict a levelized cost of hydrogen as low as 2 €/kg for electrolysis plants operating at a scale of hundreds of MW, with an electricity cost of 40 €/MWh [4]. As thermal management is a pivotal aspect of SOE stack durability and system operability, our study focuses on the thermal aspects during stack operation. The CEA has developed a compact R&D SOE stack architecture that precludes local temperature measurements, despite the critical importance of thermal mapping for optimal stack operation. To address this, CEA is conducting advanced experiments on instrumented stacks alongside numerical modeling efforts. These experiments aim to deepen our understanding of stack thermal behavior and validate thermal models with experimental data. The compact stack design, as presented in [5], uses thin AISI441 ferritic stainless steel interconnects. A nickel-mesh and an LSM layer (Lanthanum-Strontium Manganite) are used as contact elements. Sealing is achieved with a commercial ceramic glass and a mica foil ensures electrical insulation and completes the sealing. This stack design is extensively described in [6] and can be assembled in a reliable way with initial performances showing very low variability [7] and the ability to be scaled up [8]. Experimental Setup for the Thermal Test on a 22-Cell Stack The experimental setup involves the insertion of additional thermocouples within the stack (Fig-1). To facilitate this, three specialized plates were designed, each supporting 14 thermocouple placements. These plates were integrated at a quarter, half, and three-quarters of the height of a standard compact CEA stack (22 cells, 200 cm² surface area). However, the 5 mm thick plates introduce additional heat exchanges via conduction and radiation, impacting the stack's temperature distribution. Thus, the reported thermal gradients are underestimated compared to the actual gradients within the stack cells. Complementary simulation work is essential to fully understand the cell thermal gradient. The stack is also equipped with standard instrumentation, including 4 thermocouples at each end plates and 4 additional thermocouples in the gas inlets and outlets. The protocol included standard solicitations to monitor temperatures within the acquisition plates and compare them with standard instrumentation readings (end plates and gas inlets/outlets). Specific tests were conducted to correlate results with numerical models, such as a thermalized polarization curve. This curve, obtained by ensuring thermal stabilization at each current step, is useful for fitting numerical models and assessing their accuracy. It avoids dynamic thermal phenomena and leads to highly endothermal or exothermal points, presumably causing significant temperature changes within the stack. At the end of the test, the stack was subjected to a highly endothermal operating point to assess its resistance to such stress and observe the thermal maps. Significant temperature gaps were then measured: up to 40°C horizontally and 55°C vertically, which are the highest temperature gaps observed during the test, and which were maintained over a hundred hours of operation. Results Stack stability Despite the harsh thermal gradients induced by heat generation during the tests and which are detailled bellow, the integrity of the stack was not compromised. The stack's performance remained consistent before and after the thermal tests, ensuring easier data analysis. Dynamic Polarization Curves This experiment highlighted the impact of current ramps on thermal maps during polarization curves. For instance, the same U-turn IV curve (700°C – 18 Nml/min/cm² 90/10 H 2 O/H 2 ) was conducted with ramps of 300 A/min and 100 A/min. Both ramps caused a temperature drop, more pronounced with the 100 A/min ramp. The 100 A/min ramp resulted in a drop of up to -12°C at the stack's center and -3°C in the end plates (Fig. 1), while the 300 A/min ramp caused drops of -5°C at the center and -1°C in the end plates. This confirms that an IV curve is not isothermal, even at high current ramps. Thermalized Polarization Curve The thermalized polarization curve was conducted at 750°C (Fig-2). Thermal maps revealed significant temperature differences within the thermal plates (horizontal gradient) and between the stack's middle and end plates (vertical gradient). At the most endothermal point (-13.4 W), the maps showed a deltaT of up to 37°C within the middle plate (maximum horizontal stabilized gradient) and 40°C between the middle and end plates (maximum vertical stabilized gradient). The temperature evolution indicated that the most homogeneous point was achieved at an endothermal operating point (~1.27 V average voltage). Endothermal Operating Point It was valuable to test the stack at an operating point inducing significant thermal gradients. This approach evaluated the effects of a sudden transition from a thermoneutral point to a high thermal power point and assessed potential degradation once stabilized. An endothermal point at 800°C with an average voltage of 1.06 V, resulting in a thermal power of -19.4 W/cell, was selected. Thermal stabilization was quickly achieved without stack failure, revealing a 55°C temperature gap between the hottest (785°C on the lower end plate) and coldest (730°C on the middle acquisition plate) points. A temperature difference of 34°C was observed within the central acquisition plate. The stack was maintained in this state for 120 hours without performance degradation or evolution of the thermal map. Discussion During polarization curves, temperature variations can be significant depending on the current ramp, questioning the use of IV curve characterization. While IV curves are useful for stack health diagnostics and performance assessment under identical conditions, assuming they are isothermal can be misleading, especially for modeling adjustments. Such curves are influenced by transient thermal effects that are highly dependent on stack architecture. Since the stack's thermal state affects its response to electrical loading, these transient effects do not reflect steady-state performance. Therefore, IV curves are valuable for assessing stack performance for a given design but must be used cautiously when comparing different stack architectures and should be conducted under identical current ramp conditions. The thermalized polarization curve provides a reliable stack signature by avoiding dynamic phenomena. The temperature evolution indicated that the "stack thermoneutral point" does not fully align with the cell electrochemical thermoneutral value, meaning the operating point which lead to a stack as homogeneous from a thermal point of view as possible while being under charge , does not fully align with the thermoneutral voltage value derived from classical thermodynamic reasoning. Such a discrepancy is most probably due to parasitic thermal resistances not accounted for in the stack voltage measurement that however contribute to the stack's thermal balance. In this particular test, a setup issue led to degradation of the current rod fixation, which became a localized but intense heat source, with temperatures up to 1000°C at high current operating points. Additionally, the stiffness disparity between the interconnects and the acquisition plates, along with the addition of new interfaces, can increase the risk of parasitic contact resistances, particularly above and below the acquisition plates. During the stabilized polarization curve or at the endothermal point, significant temperature differences were measured: up to 40°C horizontally and 55°C vertically. Despite extreme solicitations, the stack did not break or degrade. These gradients may be considered acceptable for the stack and could represent the lower limit of tolerable thermal gradients. However, further work is required to decouple these values from the stack architecture and loading setup parameters to generalize this value for other stacks. Throughout these thermal tests, the discrepancy between the temperatures at the end plates and those at the core of the stack was significant (up to 9°C on a dynamic polarization curve and up to 55°C at a stabilized point). The thermal impact of the 5 mm thick acquisition plates on the thermal maps has not been fully evaluated, but the temperature differences at the cell level are likely greater than those measured. Ongoing simulation work aims to adjust the model and interpret these thermal results comprehensively. If this work has demonstrated the relevance of accurate thermal mapping for SOE stacks, instrumenting all stacks with this type of thermal plate is undesirable due to the complexity and bulkiness of implementation. Therefore, it is essential to continue refining our detailed understanding of temperature field distributions and their origins within the stack through experimental tests and modeling. Acknowledgements This project is carried out in collaboration with GENVIA. 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