HAD:A Prototype Of Dataflow Compute Architecture

Abstract To investigate the features, implementation, and applications of data flow architecture, a novel dataflow computing system, HAD (Hardware Accelerated Dataflow), is proposed. This system enhances the traditional control flow processor by integrating a dataflow component.HAD introduces two specialized instructions to the RISC ISA and provides OS system calls for applications. Users can execute programs that adhere to the dataflow execution model on the system, enabling synchronization and mutual exclusion between processes through the inherent characteristics of dataflow computing.We further analyze how our dataflow computing can reduce the overhead of OS system calls for synchronization and mutual exclusion between processes.Lastly, we perform simulations using Verilator, implement the system on an FPGA device based on the RISC-V prototype architecture, and transplant a miniature operating system for it. We evaluate its performance using EPCC Microbenchmarks. The simulation and physical experiment results indicate that when the number of processes is substantial, the system exhibits a time reduction of up to 29\% compared to the traditional approach. The simulation results closely correspond to the actual outcomes.