Heterogeneous System-in-Package (HSIP) Using Fan-Out Wafer-Level Packaging (FOWLP)

An interposer with embedded semiconductor die and passive devices has been fabricated using a Heterogeneous System-in-Package (HSIP) technology in order to create a highly dense integrated multi-chip module (MCM) package solution. This technology is based on Fan-out Wafer-level Packaging (FOWLP) technology which consists of a molded core wafer having embedded devices, through mold vias (TMVs), and passive devices, along with buildup circuitry layers on both sides of the molded core wafer. This HSIP technology is capable of integrating multiple die and passives to achieve maximum device packing, which are molded using an epoxy based silica filled molding compound to create a reconstituted wafer. In order to maintain a flat module, it is necessary to balance the amount of Cu in both the front and back layers to achieve a neutrality of the module bow during thermal excursions. To create the buildup layers, a first dielectric material is deposited over the reconstituted wafer, vias are created and then the Cu circuitry is formed. This sequential process is repeated until the required number of layers is formed. This same process is repeated on the backside of the wafer. After the buildup layers are produced on the molded wafer, the individual modules are diced out of the wafer. On both sides of the outer layers are ball grid array (BGA) pads which allow these modules to be stacked using conventional solder attach methods. The completed individual HSIP modules are relatively thin packages, which average about 350um. This HSIP technology can produce a robust package design that can meet aggressive JEDEC testing requirements for military, aerospace and commercial applications, in order to achieve the lowest power consumption, weight and size. A discussion of our HSIP technology will be presented along with supporting reliability data.