Low-power cordic multiplier design using approximate arithmetic for energy-efficient computing

In digital IC design, low-power CORDIC-based multipliers have attracted significant attention due to their potential to integrate approximate adders for reducing energy and area costs. While CORDIC is hardware-efficient, its precise design still has room for improvement, particularly in terms of power consumption and area overhead. To address this, we present an approach to enhance the CORDIC multiplier using Approx. Adders from the EvoApproxLib library. The proposed design offers multiple variants with different optimization targets: up to 19.3% power reduction in CORDIC + Approx. Adder, 11.5% area savings in CORDIC + Approx. Adder, and 14.7% frequency improvement in CORDIC + Approx. Adder compared to the conventional exact CORDIC multiplier. When applied to Gaussian filtering and Sobel edge detection, optimal variants such as CORDIC + Approx. Adder and CORDIC + Approx. Adder yield PSNR values of 60 and 48 dB respectively, with SSIM values exceeding 0.990, indicating minimal quality loss. The evaluation shows that 8–10 iterations provide the best efficiency-accuracy trade-off, enabling designers to select appropriate variants based on specific application requirements. These results demonstrate the effectiveness of the proposed method for energy-constrained, error-tolerant systems in IoT devices, edge computing, and image processing applications