Wireless Network-on-Chip for Multi-Die Systems

High performance computing and the need for processing power have cultivated increasing number of on-chip processing elements (PEs), therefore increasing the total overall area. The increase in distance has a negative effect in packet latency, congestion, and total throughput of the system. Network-on-Chip (NoC) is the de facto communication infrastructure for these large scale processors. Wireless NoCs, through the inclusion of on-chip antennas, are introduced to improve the performance of long-distance communication within a package. On-chip wireless interconnects offer improved network performance due to improved long distance communication, additional bandwidth, and broadcasting capabilities of antennas. This dissertation challenges the on-chip antenna design conventions, and pushes toward a Through-Silicon Via (TSV)-based antenna design called "TSV_A" that establishes multi-band wireless communication for computing packages. Finite element method simulations, printed circuit board prototyping, and system-level network simulations show that TSV_A is the perfect candidate for improved signal performance and flexibility in design and implementation. Comparisons to traditional wire-based NoCs, technology scaling to demonstrate the substantial area improvements, and analysis of wireless multi-bands are performed. In addition, this dissertation introduces a scalable interconnect infrastructure for multi-die system with multiple 3D chiplets connected through an active interposer and compatible with TSV_A.