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Low-Temperature Preparation of Ferroelectric Sr2(Ta1-x,Nbx)2O7 Thin Films by Pulsed Laser Deposition and Their Application to Metal-Ferroelectric- Insulator-Semiconductor-FET

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Sr2(Ta1-x ,Nb x )2O7(STN) ferroelectric thin films have been prepared on SiO2/Si(100) substrates by the pulsed laser deposition (PLD) method. Preferential (110) and (151)-oriented STN thin films were deposited at a low temperature of 600°C in N2O ambient gas at 0.08 Torr. A counterclockwise C–V hysteresis was observed in the metal-ferroelectric-insulator-semiconductor (MFIS) structure using Sr2(Ta0.7,Nb0.3)2O7 on SiO2/Si deposited at 600°C. The memory window in the C–V curve spreads symmetrically towards both positive and negative directions when the applied voltage is increased and the window does not change in sweep rates ranging from 0.1 to 4.0×103 V/s. The C–V curve of the MFIS structure does not degrade after 1010 cycles of polarization reversal. The gate retention time is about 3.0×103 s when the voltage and time of write pulse are ±15 V and 1.0 s, respectively, and the hold bias is -0.5 V.
Title: Low-Temperature Preparation of Ferroelectric Sr2(Ta1-x,Nbx)2O7 Thin Films by Pulsed Laser Deposition and Their Application to Metal-Ferroelectric- Insulator-Semiconductor-FET
Description:
Sr2(Ta1-x ,Nb x )2O7(STN) ferroelectric thin films have been prepared on SiO2/Si(100) substrates by the pulsed laser deposition (PLD) method.
Preferential (110) and (151)-oriented STN thin films were deposited at a low temperature of 600°C in N2O ambient gas at 0.
08 Torr.
A counterclockwise C–V hysteresis was observed in the metal-ferroelectric-insulator-semiconductor (MFIS) structure using Sr2(Ta0.
7,Nb0.
3)2O7 on SiO2/Si deposited at 600°C.
The memory window in the C–V curve spreads symmetrically towards both positive and negative directions when the applied voltage is increased and the window does not change in sweep rates ranging from 0.
1 to 4.
0×103 V/s.
The C–V curve of the MFIS structure does not degrade after 1010 cycles of polarization reversal.
The gate retention time is about 3.
0×103 s when the voltage and time of write pulse are ±15 V and 1.
0 s, respectively, and the hold bias is -0.
5 V.

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