A Highly Reliable Reconfigurable SRAM PUF Based on Error Correction Codes and Capacitor Preselection

In recent years, researchers have extensively utilized the inherent variations occurring during the manufacturing process of integrated circuits to create physical unclonable functions (PUFs) as hardware security primitives. However, traditional static entropy sources employed in PUF applications exhibit certain drawbacks, including limited availability of challengeresponse pairs (CRPs) and inadequate randomness. Additionally, the reliability of PUFs is compromised due to the impact of temperature and voltage fluctuations as well as aging effects. To address these issues, this article presents a novel architecture for PUFs based on Static Random Access Memory (SRAM) along with a more suitable error-correcting code (ECC). Our approach enhances the reliability of SRAM-based PUFs both internally, through capacitor preselection, and externally, by employing ECC. The coding and decoding process of the ECC is elaborated in detail. Furthermore, we analyze the relevant parameters of the ECC and demonstrate that the combination of these techniques results in a final bit error rate (BER <0.1%). Through calculations, we validate that our reconfigurable SRAM PUF can yield a larger number of CRPs. Experimental results conducted on Xilinx Artix 7 demonstrate that the ECC we employ achieves an ideal BER for PUFs, while simultaneously reducing hardware overhead by 80%.