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Towards the Fabrication of Ultra-Thin SOI on Si (001) using Epitaxial Oxide and Epitaxial Semiconductor Growth Processes
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Silicon on insulator (SOI) substrates will be required to reduce capacitive coupling and other parasitic effects as device scaling continues. ITRS projections point to a future need for SOI buried oxide layers as thin as 10 nm, and Si channel thickness potentially as low as 5 nm for fully- depleted ultra-thin-body devices. For such thin layers, conventional SOI fabrication processes become increasingly difficult. Progress towards fabricating ultra-thin SOI on Si (001) through an all-growth approach is presented. All steps are performed sequentially in situ, with no wet chemical processing. Starting with a Si wafer as large as 8 , our approach is to: 1) deposit a thin commensurate epitaxial oxide layer such as Ca1-xSrxTiO3; 2) oxidize to grow an interface SiO2 layer ('floating' the epitaxial oxide) for stress relief and lowering of the dielectric constant; and 3) deposit epitaxial Si or Si1-xGex to complete the fabrication process.
The Electrochemical Society
Title: Towards the Fabrication of Ultra-Thin SOI on Si (001) using Epitaxial Oxide and Epitaxial Semiconductor Growth Processes
Description:
Silicon on insulator (SOI) substrates will be required to reduce capacitive coupling and other parasitic effects as device scaling continues.
ITRS projections point to a future need for SOI buried oxide layers as thin as 10 nm, and Si channel thickness potentially as low as 5 nm for fully- depleted ultra-thin-body devices.
For such thin layers, conventional SOI fabrication processes become increasingly difficult.
Progress towards fabricating ultra-thin SOI on Si (001) through an all-growth approach is presented.
All steps are performed sequentially in situ, with no wet chemical processing.
Starting with a Si wafer as large as 8 , our approach is to: 1) deposit a thin commensurate epitaxial oxide layer such as Ca1-xSrxTiO3; 2) oxidize to grow an interface SiO2 layer ('floating' the epitaxial oxide) for stress relief and lowering of the dielectric constant; and 3) deposit epitaxial Si or Si1-xGex to complete the fabrication process.
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