Design and Implementation of a Multi-stage Pipelined Hardware for RoadRunner Lightweight Block Cipher

Abstract RoadRunner is an efficient block cipher developed for lightweight platforms. This paper discusses the design and implementation of pipelined hardware for RoadRunner on Field Programmable Arrays (FPGAs). The cipher’s Feistel round function loops are unrolled, and the outers rounds are pipelined to increase the throughput. The hardware architecture of the design is fully pipelined in 12 stages for optimum performance and area utilization. Comparing with the existing non-pipelined implementations of the same cipher, our work achieves much higher throughput of 7742 Mbps and an efficiency of 2.1 Mbps per slice on the same FPGA. Comparisons with other similar cipher implementations are also analyzed in this work.