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Design of 3780 Points FFT Processor for DTMB Receiver
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In this paper, a design of FFT processor for Digital terrestrial multimedia/television broadcasting (DTMB) receiver is presented. This processor is based on mixed-radix algorithms, prime factor algorithms and Winograd Fourier Transform algorithm (WFTA). Due to the adopted in-place algorithm in this design, the area consumption of the processor is reduced, and the simulation shows that SQNR of the processor is 60.5dB on the condition that the input and output data are both 13 bits.
Title: Design of 3780 Points FFT Processor for DTMB Receiver
Description:
In this paper, a design of FFT processor for Digital terrestrial multimedia/television broadcasting (DTMB) receiver is presented.
This processor is based on mixed-radix algorithms, prime factor algorithms and Winograd Fourier Transform algorithm (WFTA).
Due to the adopted in-place algorithm in this design, the area consumption of the processor is reduced, and the simulation shows that SQNR of the processor is 60.
5dB on the condition that the input and output data are both 13 bits.
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