Heterogeneous System-In-Package (HSIP) Technology

Abstract A stitched test vehicle has been designed using molded wafer technology to characterize the assembly yield and reliability of a 4-layered topside Buildup (BU) and 4 layered bottom side BU package. In this design, the individual module uses 20 1mm square Si die elements, and one 10mmm square Si die and 8 through substrate vias (TSVs) arrayed on a 14mm square module size to produce a Reliability Test Vehicle (RTV) using Fan-out Wafer-Level (FOWL) technology. 17 individual RTV modules are molded on a 100mm wafer to create a reconstituted wafer. On the 1mm square Si die are two dog bone structures that allows for the design of a stitched net for each build layer with the embedded Si die. Therefore one can generate a stitched net between the first BU layer with the embedded Si die, the second BU layer with the embedded die layer, and so on. The layered stitched design feature, allows one to characterize the integrity of the individual BU layers during the sequential BU processing of the layers on both sides of the molded core. The TSVs allow for signal communication between the top 4 BU layers with the 4 backside BU layers. On top of each 4th layer is a ball grid array (BGA) pad on a 0.8mm pitch that can be used to stack this module using conventional soldering methods. This approach to embed die in a molded wafer and then BU layers on each side is referred to as Heterogeneous System-in-Package (HSIP) technology. Another feature to be included in this work is the use of Current Induced Thermal Cycle (CITC) testing. This is a fast and accurate test method developed by i3 Electronics in Endicott, NY to assess the reliability of vias in a BU package. It is widely used in the industry for circuit boards and build up organic substrates, and is now be applied to the finer via dimension (25um diameter) used for HSIP technology. As was discussed above for the RTV design, the same BU and TSV features will be tested in this CITC module design. The BU layers are exactly the same as that used in the above RTV design. For this wafer build, the die will be molded to create a reconstituted wafer. The first goal is to develop a molding process that has less than 20um die shift and produces a molded substrate with the acceptable amount of bow to accommodate the topside build up layers. For each BU layer, the assembly yield can be characterized by probing the stitched nets for the first, second, and so on BU layers for both sides. This data will provide assembly yield. The individual RTV and CITC modules can then be diced from the wafer, solder balls are attached to the topside BGA pads, and then tested using a conventional clam shell socket test fixture. The first set of reliability tests will be thermal cycling and temperature humidity. In this paper we will discuss the challenges with building HSIP modules, their yield and the first phase of reliability testing.