In Process Stress Analysis of Flip Chip Assemblies During Underfill Cure

Abstract The electronics industry is currently evaluating flip chip technology for high performance, miniaturized assembly applications. This is primarily because of the high I/O density, small form factor, and superior electrical performance provided by flip chip on board technology. Flip chip on low cost circuit boards (FCOB) furnishes a reliable interconnection provided underfill materials are used. Underfills overcome the thermomechanical reliability issues associated with the thermal expansion coefficient mismatch between the board and die. The selection of underfill material is critical to achieving the desired performance and reliability. Processing of underfills during assembly can result in large residual stresses within the silicon die. In some instances these stresses can be large enough to cause die fracture. In this work, low cost flip chip on board assemblies are analyzed during the underfill cure process. In situ stress measurements are performed over the active face of the die during processing and relative in-plane stresses are measured. Experimental measurements are made using flip chip test vehicles based on Sandia National Laboratories’ ATC04 Assembly Test Chip. Four different commercial underfill materials have been evaluated and a relative comparison is presented. Significant stress variations are observed between the four underfills studied. Correlation’s between the glass transition temperature (Tg) and storage modulus (G’) are made relative to residual stresses produced during underfill cure.