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Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology.
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For high speed application the static random access memory is mostly demandable. Such kind of device should possess additive parameters that can withstand during transistor scaling process. Their exist static noise margin (SNM) which degrades the device performance of memory architectures, majorly observed at write and read operation create write noise margin (WNM) and read noise margin (RNM). In this paper we discuss about the basic design of 6 transistor SRAM (6T SRAM) using 180nm and 45nm CMOS technology in Cadence Virtuoso with write noise margin analysis. The propagation delay, power dissipation, WNM are measured for both the technologies and observed that WNM is relatively low in 45nm.
Title: Estimation of Write Noise Margin for 6t SRAM Cell in CMOS 45nm technology.
Description:
For high speed application the static random access memory is mostly demandable.
Such kind of device should possess additive parameters that can withstand during transistor scaling process.
Their exist static noise margin (SNM) which degrades the device performance of memory architectures, majorly observed at write and read operation create write noise margin (WNM) and read noise margin (RNM).
In this paper we discuss about the basic design of 6 transistor SRAM (6T SRAM) using 180nm and 45nm CMOS technology in Cadence Virtuoso with write noise margin analysis.
The propagation delay, power dissipation, WNM are measured for both the technologies and observed that WNM is relatively low in 45nm.
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