SYNCHRONOUS-TO-ASYNCHRONOUS CONVERSION OF CRYPTOGRAPHIC CIRCUITS

This paper introduces a novel method for the conversion of synchronous cryptographic circuits into equivalent asynchronous ones. The new method is based on ASERT (Asynchronous Scheduling by Edge Reversal Timing), a fully decentralized timing signaling and synchronization algorithm. From a synthesizable HDL code, an asynchronous timing network, made from standard cells libraries, is generated in order to replace the clock tree of the target circuit. ASERT works with matched delays, local clocks or any equivalent way of determining, statically or dynamically, the operating time of each functional unit. Synchronous to asynchronous conversion of three different cryptographic circuits, including the fully synthesized netlists of AES, Reed-Solomon decoder, and RSA cipher cores, are presented.