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Reconfigurable Negative Bit Line Collapsed Supply Write Assist for 9T-ST SRAM Cell
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Abstract
This paper presents a Reconfigurable Negative Bit Line Collapsed Supply (RNBLCS) write driver circuit for the 9T Schmitt Trigger-based SRAM Cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in Write Static Noise Margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in Write Margin (WM), 0.96×, 0.89× and 0.72× minimum Write Trip-Point (WTP) from Transient-Negative Bit Line (Tran-NBL), capacitive Charge Sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a Synopsys Custom compiler with a 16nm BSIM4 model card for bulk CMOS.
Title: Reconfigurable Negative Bit Line Collapsed Supply Write Assist for 9T-ST SRAM Cell
Description:
Abstract
This paper presents a Reconfigurable Negative Bit Line Collapsed Supply (RNBLCS) write driver circuit for the 9T Schmitt Trigger-based SRAM Cell (9T-ST), significantly improving write performance for real-time memory applications.
In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability.
The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.
84×, 0.
48×, 0.
27× optimized write access delay and 1.
05×, 1.
08×, 1.
19× improvement in Write Static Noise Margin (WSNM), 1.
05×, 1.
13×, and 1.
39× improvement in Write Margin (WM), 0.
96×, 0.
89× and 0.
72× minimum Write Trip-Point (WTP) from Transient-Negative Bit Line (Tran-NBL), capacitive Charge Sharing (CCS), and conventional write circuits respectively.
The proposed RNBLCS is functionally verified using a Synopsys Custom compiler with a 16nm BSIM4 model card for bulk CMOS.
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