Component and Board Level Reliability of High Pin Count Flip Chip Packages

ABSTRACT This paper presents recent results on component and board level reliability of high pin count flip chip packages, which are of increasing interest due to the high growth of high-end applications. Effects of substrate material, environmental testing, mechanical layout, and stress field on the component and board level reliabilities were widely investigated. Results of this extensive study aimed at developing high pin count flip chip packages with good electrical performance. Mechanical modeling with Finite Elementary Method (FEM) and package warpage analysis with shadow moire measurement demonstrated the nature of stress field in the package and its shift during assembly and environmental stress testing. Two kinds of bump pitches (200 μm and 250 μm) and two kinds of substrates (high performance laminate and buildup) were used in the flip chip package development and qualification. Reliability behavior of solder joints depends on the their locations in the packaging. The bumps and joints could be in a Z direction displacement dominated field in addition to a conventional X/Y shear displacement dominated field induced by a mismatch of coefficients of thermal expansion (CTE) among the packaging materials. Reliability testing results on these packages also showed that traditional failure models on Ball Grid Array (BGA) package failed to fully explain the reliability behavior of high pin count flip chip packages, which accompanied frequently with large body size. More dedicated model based on the reliability physics of solder bump and solder joint needs be developed.