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A Novel Silicon/MAPbI3-based Heterostructure Field-Effect Transistor
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Abstract
In this article, we propose the use of a Silicon/APS/MAPbI
3
Heterostructure in a field-effect transistor for the first time. In the proposed transistor, APS molecules are employed as linkers between silicon and MAPbI
3
to improve the interface properties. Our results indicate that a transistor based on this heterostructure provides suitable electrical performance. Such performance, along with the simplicity and low-cost fabrication process, could expand the use of this transistor in various applications. The simulations take into account the influence of the trap density of states on carrier mobility at the silicon surface, which constitutes a critical factor in limiting the performance of the transistor. The effect of linker molecules on the silicon surface is incorporated through interfacial traps and shifts in the silicon surface Fermi level. The effect of barrier-layer thickness on the proposed transistor characteristics is also examined by analyzing three device configurations with barrier widths of 5 nm, 10 nm, 20 nm and 30 nm. The calculated result for threshold voltages is 0.1 V, − 0.3 V, -1.1 V and − 1.9 V for these structures, respectively. Furthermore, we investigate the frequency response of the device, demonstrating that a current-gain cutoff frequency of up to 35 GHz can be achieved. In this study, we also perform a comparison between carrier-transport results obtained using the Density Functional Tight Binding (DFTB) method and those derived from drift–diffusion–based simulations enhanced with appropriate physical models to improve computational accuracy.
Title: A Novel Silicon/MAPbI3-based Heterostructure Field-Effect Transistor
Description:
Abstract
In this article, we propose the use of a Silicon/APS/MAPbI
3
Heterostructure in a field-effect transistor for the first time.
In the proposed transistor, APS molecules are employed as linkers between silicon and MAPbI
3
to improve the interface properties.
Our results indicate that a transistor based on this heterostructure provides suitable electrical performance.
Such performance, along with the simplicity and low-cost fabrication process, could expand the use of this transistor in various applications.
The simulations take into account the influence of the trap density of states on carrier mobility at the silicon surface, which constitutes a critical factor in limiting the performance of the transistor.
The effect of linker molecules on the silicon surface is incorporated through interfacial traps and shifts in the silicon surface Fermi level.
The effect of barrier-layer thickness on the proposed transistor characteristics is also examined by analyzing three device configurations with barrier widths of 5 nm, 10 nm, 20 nm and 30 nm.
The calculated result for threshold voltages is 0.
1 V, − 0.
3 V, -1.
1 V and − 1.
9 V for these structures, respectively.
Furthermore, we investigate the frequency response of the device, demonstrating that a current-gain cutoff frequency of up to 35 GHz can be achieved.
In this study, we also perform a comparison between carrier-transport results obtained using the Density Functional Tight Binding (DFTB) method and those derived from drift–diffusion–based simulations enhanced with appropriate physical models to improve computational accuracy.
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