Evolution of Nanotechnology Using Quantum Dot Cellular Automata

Abstract The use of Quantum-dot Cellular Automata (QCA) has come to light as a promising nanoelectronic technology that can surpass the scaling restrictions, high power consumption and area of the Complementary Metal Oxide Semiconductor (CMOS) circuits. In this chapter, compact QCA-based combinational and sequential circuits are designed and analyzed for performance, with a particular focus on an optimized D-latch and memory architecture based on SRAM. QCA Designer 2.0.3 is used to implement and analyse fundamental QCA logic gates, multiplexers and memory structures. The single-layer QCA D-latch is realized with just 14 cells, the cell layout area 0.007 µm² and the clock latency 0.5 cycles. The proposed structure results in approximately 21% reduction of layout area as compared to the existing QCA latch design, 20% increase in operational speed and nearly 49.6% reduction in overall QCA cost when compared to the existing QCA latch design. Moreover, a new 15-cell QCA D-latch with embedded SET and RESET is suggested which consumes almost 22% less energy dissipation and has an area of 0.0048 µm² for SRAM application. A comparative study with available QCA and CMOS memory architectures shows that their compactness, power consumption, and scalability are significantly improved. The simulation results obtained confirm stable logic propagation, data reliability in memory, and efficient operation of memory devices, all of which show that QCA technology is suitable for the development of next-generation ultra-dense low power nanoelectronic systems and memories.