Gated-V<Sub>Dd</Sub> Based Single Ended Sram Arrays

Latching to store a bit of information. As the size of CMOS technology scales down to deep submicron region, power dissipation becomes a major issue in the VLSI design. The leakage power becomes dominant due to the second order effects of the transistors in deep submicron region. The leakage power aids in considerable increase of the total power dissipation of the device. The existing SRAM cells at submicron region dissipate more power and become unstable inspite of applying low power techniques like multi-threshold logic, body biasing techniques, stacked structures etc. This paper concentrates on the design of stable single ended SRAM array using power gating technique. The designs are developed and analyzed for different nm technologies using Digital Schematic and Microwind Tools. By using same tools, the Gated VDD technique based SRAM is analyzed to reduce the leakage power. The reduction in voltage swing results in reduction of dynamic power dissipation. The SRAM arrays for 2x2 and 4x4 arrays were developed using both 5T (or single ended) and Gated VDD 5T SRAM cells. The power dissipation at 90nm technology is reduced by 35% and 55.3% for gated 2x2 and 4x4 SRAM arrays respectively, when compared to single ended 2x2 and 4x4 SRAM arrays.