The improved 2DoFs-PLL for MMC-HVDC transmission system

The performance of a modular multilevel converter (MMC) is highly related to the three-phase phase-locked loop (PLL). The presence of the DC component, the harmonic component, and the negative sequence component results in the poor dynamic and steady-state performance of the PLL, such as fundamental frequency oscillations in the phase estimated by the PLL. In order to suppress the influence of parameters variation and disturbance of the three-phase grid voltage, an improved PLL with a moving average filter with two degrees of freedom PID (2DoFs-PID) is proposed. Moreover, to improve the phase margin and gain margin, an extra compensator with a pole and a zero is introduced into the 2DoFs-PLL. The improved 2DoFs-PLL can track the frequency and phase with superior accuracy, stability, and rapidity. Furthermore, the methodology for the parameters design of the 2DoFs PID controller is introduced, based on the index of integrated time and absolute error. A simulated model and experimental platform are established to verify the performance of the improved 2DoFs-PLL. The results show that the improved 2DoFs-PLL can meet the needs of both steady-state performance and dynamic performance by employing the 2DoFs-PID controllers.