(Plenary) Substrate Innovation for Extending Moore and More than Moore Law

Within last 10 years, end markets drastically changed towards mobile connected users. With 8B smartphones to be shipped next 4 years, typical performance/cost KPIs have been evolved towards more demanding PPAC metrics adding power consumption (battery life) and area (from factors) constraints. Since 28nm, device roadmap has been deviated with more complexity to cope with new targets, including a revolutionary shift towards FinFET devices reaching unprecedented die cost increase (Table1 [1]). In this effort to bring more performance, less power or more functionality, innovation or evolution starting from substrates has demonstrated significant successes. In the field of front end modules (FEM) for smartphones, switch, previously built on AsGa substrates, are now built on RFSOI substrates. RFSOI substrate offer a high resistivity handle wafer, isolated from standard resistivity active layer thru buried oxide layer. Then, while device designed on SOI is delivering competitive Ron.Coff parameters, RF linearity is guaranteed by harmonics absorption from handle wafer. Compared to 150mm AsGa wafers, 200mm RFSOI wafers are silicon family wafers and FEM switch are now built in large volume in most foundries, offering very significant die cost advantage. Latest RFSOI products are even pushing further handle wafer effect on device performance with eSi substrate (enhanced Signal Integrity), boosting switch, antenna tuner and even power amplifiers towards meeting advanced LTE specifications (figure 2). Still for mobile applications, UTBB (Ultra-Thin Box and Body) substrates are enabling extension of Moore’s low after 28nm, keeping the same cost benefit from shrinking to 20nm and even 14nm nodes. After several years of R&D, Smart-Cut technology is now capable of generating ultrathin silicon layers on ultrathin buried oxide layers with Å level uniformity control. Such thin and controlled silicon thin can directly be used as channel, undoped, for 28nm FDSOI design (figure 3). Leveraging a back gate control thru ultrathin BOX of these substrates, the 28FDSOI devices can quickly switch from low power to high performance modes and meet highest Power/Performance combinations [2]. FDSOI substrate roadmap is supporting 3 nodes, from 28nm down to 10nm (FD28, FD14 and FD10). In the case of last node, a new benefit is introduced into active layer form performance increase with strain silicon layer that is allowing nMOS acceleration. FDSOI cost analysis case is right example on how starting from an SOI wafer can lead to a cheaper die. Lithography cost is drastically increased node after node and is driving-up individual process steps cost. Depending on SOI design options and node, multiple process steps can be saved (implantation, isolation) and, from 28nm node, they more than compensate starting substrate price gap. Not even considering yield benefit from less processing steps, finished FDSOI processed wafer is less expensive than same design built on bulk silicon. With more performance, less power consumption, and less cost, FDSOI device are very compelling option for low end, mid range mobile applications, but also IOT devices coming large volumes. These 2 examples can be reproduced for many other application fields or device options. Substrate innovation is supporting major improvements in Silicon Photonics, Image sensors, MEMS, new generation FinFET, with always same ability to bring more with opportunity for less final cost, which is key for our world, driven by more mobility and more data. [1] H. Jones, IBS, 2014 FDSOI Forum, Shanghai, China. www.soiconsortium.org/fully-depleted-soi/presentations/september-2014-fd-soi-forum/ [2] J.M. Chery, ST, "Highly Energy Efficient Nanotechnologies and Applications", Semicon Grenoble Low Power Conference 2014. Figure 1