Analysis and Improvement of Retention Time of Memorized State of Metal-Ferroelectric-Insulator-Semiconductor Structure for Ferroelectric Gate FET Memory

Retention characteristics of metal-ferroelectric-insulator-semiconductor (MFIS) structures have been studied theoretically by considering effects of charge injections derived from the difference between leakage current densities in the ferroelectric and insulator layers. The calculated curves for time-dependent capacitance have shown good agreements with experimental results. The numerical results for the MFIS structure have indicated that excess current over a certain value through the ferroelectric and the insulator layers causes the retention time to rapidly degrade. An idea of inserting an insulator film between the metal and the ferroelectric layers in an MFIS has also been examined in order to cut down the currents through the ferroelectric layer. The calculations based on our model have found this metal-insulator-ferroelectric-insulator-semiconductor (M-I-FIS) structure to exhibit much longer retention time than the conventional MFIS.